Electrical components such as resisters, capacitors, inductors, transistors, integrated circuits, and chip carriers are typically mounted on circuit boards according to one of two configurations. In the first configuration, the components are mounted on one side of the board and leads from the components extend through holes in the board and are soldered on the opposite side of the board. In the second configuration, the components are soldered to the same side of the board upon which they are mounted. These latter devices are said to be “surface-mounted.”
Surface mounting of electronic components is used to fabricate small circuit structures and lends itself well to process automation. A type of surface-mounted device referred to as an area array package comprises an electronic component such as an integrated circuit having numerous connecting leads attached to pads mounted on the underside of the device.
Examples of area array packages include a flip chip, a chip scale package (CSP), and a ball grid array (BGA). In connection with the use of an area array package, either the circuit board or the device is provided with small bumps or balls of solder (hereinafter “bumps” or “solder bumps”) positioned in locations which correspond to the pads on the underside of each device and on the surface of the circuit board. The device is mounted by (a) placing it in contact with the board such that the solder bumps become sandwiched between the pads on the board and the corresponding pads on the device; (b) heating the assembly to a point at which the solder is caused to reflow (i.e., melt); and (c) cooling the assembly. Upon cooling, the solder hardens, thereby mounting the device to the board. Tolerances in area array technology are critical, as the spacing between individual devices as well as the spacing between the devices and the board is typically small. For example, spacing of a flip chip from the surface of a board to the bottom of a die is typically between about 15 and about 75 microns and is expected to approach about 10 microns in the near future.
One problem associated with area array technology is that the chips, the solder, and the material forming the circuit board often have significantly different coefficients of thermal expansion. As a result of the differing expansions, the heating of the assembly during manufacture and use can cause severe stresses. Further, substantial stresses occur when devices are dropped (e.g., wireless telephones and portable computers). The stresses imposed on the solder interconnects can lead to failures that degrade device performance or incapacitate the device entirely.
In order to minimize thermomechanical fatigue resulting from different thermal expansions, thermoset epoxies have been used as an underfill material which surrounds the periphery of the area array device and occupies the space beneath the chip between the underside of the chip and the board which is not occupied by solder. Such epoxy systems provide a level of protection by forming a physical barrier which resists or reduces the stress on solder interconnects due to different expansions among the components of the device and/or to drop shocks.
Several trends have become increasingly important in the technology of area-array surface mounted devices. These include 1) increasing flip-chip and BGA die sizes, 2) increasing number of electrical interconnects, 3) decreasing gap-heights between the die and substrate, 4) a drive for increased through-put, and 5) incorporation of fragile low-K dielectric layers in the silicon die. To address these issues, there has been intense interest in the use of so-called “no-flow underfills” (NUF). These are typically thermosetting, epoxy-based materials which contain fluxing agents.
No-flow underfill is applied directly to a board before device placement. When heat is applied as in, for example, a reflow oven, the fluxing agents begin removing metal oxides on the solder balls and on the pads, which enables solder wetting and solder joint formation above the liquidus temperature of the solder. Simultaneously, the underfill begins to polymerize (cure), forming a strong adhesive layer between the die (or BGA/CSP) and the boards. This adhesive layer acts to distribute thermal stresses between the components, and thus increases the device reliability.
Existing NUF materials often exhibit undesirable properties, such as lack of sufficient fluxing ability (resulting in poor electrical yield), excessive volatility, out-gassing, or formation of bubbles or voids in the underfill layer, which can adversely affect the reliability of the device. These deficiencies are closely related to the chemistries used in NUF. For example, a typical commercial NUF is composed of a liquid epoxy resin, a anhydride curing agent (which is volatile at elevated reflow temperatures), as well as lesser amounts of a cure accelerator and additives which are either acidic (e.g. carboxylic acids), or additives which react with the anhydride to form acidic species in-situ during cure (e.g., active hydrogen compounds such as alcohols). Because of their comparatively high volatility, anhydride compounds, in particular, included in NUF materials contribute to void formation. Voids degrade the reliability of the underfill by allowing solder “bridging” to occur, especially at the high reflow temperatures needed for lead free solder applications, or by acting as stress-concentrators which lead to underfill crack growth during thermal cycling.
No-flow underfills have been prepared by mixing the epoxy resin and curing agents together until the mixture is uniform, and then any remaining constituents such as wetting agents, defoaming agents, and CTE modifiers have been dissolved or mixed into the solution.
The possibilities for designing an improved NUF having reduced voiding potential and increased fluxing activity been limited by a variety of performance requirements, such as a) good pot life and shelf life, b) acceptable viscosity to render the material dispensable, c) high Tg, d) strong adhesion to die passivation and solder mask, e) high fracture toughness K1c, f) moisture resistance, and others.